Semiconductor integrated circuits contain large numbers of electronic components such as diodes and transistors built on a single chip. Due to the microscopic scale of these circuits, they are susceptible to component defects caused by material impurities and fabrication hazards.
In order to circumvent this problem, chips are built with redundant components and/or circuits that can be switched-in in lieu of corresponding circuits found defective during testing or operation. Usually the switching-out of a defective component or circuit and the switching-in of a corresponding redundant element is accomplished by using program logic circuits which are activated by blowing certain fuse-type memory devices built into the chip circuitry. The blowing of the fuse-type memory devices is normally performed prior to packaging, burn-in and delivery. The number of redundant circuits is limited by the space available on the chip. Allocation of space is balanced between the competing goals of providing the maximum amount of primary circuitry, while maintaining adequate redundancy.
Memory chips are particularly well suited to benefit from redundancy systems since typical memory ICs comprise millions of equivalent memory cells. Each memory cell or bit can maintain a logical 1 or 0 value. The cells are divided into generally autonomous "sections" or memory "arrays". For example, in a typical 64 Mbit DRAM there are 8 sections of 8 megabits apiece.
Each section is further divided into "sub array blocks" (SAB's ) and the associated support circuitry for designating and accessing the cells within each SAB. In keeping with our example, each section of a 64 Mbit DRAM contains 8 SABs having about one million memory cells apiece. The memory cells in each SAB are arranged into an array of rows and columns. A single row or column is referred to as an "element" in this specification. A number of elements may be grouped together to form a "bank" of elements.
Over the years, engineers have developed many ingenious redundancy schemes which more efficiently use the available space on an IC. One recent scheme described by Morgan (U.S. Pat. No. 5,281,868) makes use of the fact that fabrication defects typically corrupt physically adjacent memory locations. The scheme reduces the number of fuses required to replace two adjacent columns by using one set of column-determining fuses to address the defective primary column and an incrementor for addressing an adjacent column. A problem with this scheme is that sometimes only one column is defective. Thus more columns are switched-out than is necessary to circumvent the defect.
Another problem with current common redundancy systems is that redundant elements serving one SAB are not available for use by other SABs . Providing this capability using previous techniques would have resulted in a prohibitive number of interconnection lines and switches.
Because the redundant circuitry located on each SAB was only available to replace primary circuitry on that SAB, each SAB had to have an adequate number of redundant circuits available to replace the most probable number of defective primary circuits which may occur. However, often times, one SAB will have no defects, while another has more defects than can be replaced by its redundant circuitry. In the SAB with no defects, the redundant circuitry will be unused while still taking up valuable space. The SAB having too many defects may cause the entire chip to be scrapped.
It would be desirable therefore to have a system whereby a given redundant circuit could replace any one of a number of primary circuits located within the entire section of an integrated circuit without unduly increasing circuit size and complexity.